1. Field of the Invention
The present invention relates to a liquid crystal display device, in particular, to an active matrix liquid crystal display device with a thin film transistor.
2. Description of the Related Art
In recent years, the size, weight, and power consumption of electronic device are being reduced. In the display device field, flat panel displays which are small in size, light in weight, and less in power consumption are being studied and developed as substitutes of conventional CRT (Cathode Ray Tube).
Among the flat panel display device, a liquid crystal display device has various features such as large display area, full colors, and low current and low voltage operation, and so forth. The liquid crystal display device which are currently available can be categorized according to operating systems. In particular, an active matrix liquid crystal display device has attractive features such as full- color moving picture display and high resolution.
In the active matrix type liquid crystal display device, one picture element (hereinafter referred to as a pixel) is disposed at each intersection of electrodes which are disposed in a matrix shape. In addition, one switching device disposed at each pixel so as to independently drives and controls the pixel connected thereto. For these switching devices, thin film transistors (TFTs) are practically used For example, liquid crystal display device with a diagonal length of 10 inches and pixels of 480 (height).times.640 (wide) have been used as lap top computer display devices. In addition, direct viewing type display devices with very high picture display quality and very high resolution and projection type display devices with fine pitch and very high resolution are being studied and developed.
FIGS. 28, 29, and 30 show the construction of an active matrix type liquid crystal display device using a TFT. FIG. 28 is a partial schematic diagram showing a pixel of a TFT array substrate. FIG. 29 is a circuit diagram showing an equivalent circuit of the pixel. Scan lines 2801 and signal lines 2803 are intersectionally disposed in a matrix shape over a glass substrate. A TFT 2805 is connected to a scan line 2801 and a signal line 2803. In addition, the TFT 2805 is connected to a pixel electrode 2807. Over the pixel electrode 2807, a storage capacitor electrode 2809 is formed through an insulation film. Thus, a TFT array substrate 2811 is formed. The storage capacitor electrode 2809 and the pixel electrode 2807 form a storage capacitance C.sub.s.
FIG. 30 is a sectional view showing the construction of an active matrix type liquid crystal display device. A liquid crystal display device is hereinafter referred to as an LCD. The LCD comprises a TFT array substrate 2811, an opposite substrate 2813 with opposite electrode, alignment layers 2817, and a liquid crystal layer 2815. The TFT array substrate 2811 is opposed to the opposite substrate 2813. The liquid crystal layer 2815 is disposed between the TFT array substrate 2811 and the opposite substrate 2813 through the respective alignment layers 2817.
In this device, while the scan line 2801 is selected, the TFT 2805 is turned on (power on state). Thus, with a voltage applied through the signal line 2803, a capacitance C.sub.LC of liquid crystal and a capacitance C.sub.s of the storage capacitor are formed. The C.sub.LC is formed of the pixel electrode 2807, the opposite electrode, and the liquid crystal layer 2815. On the other hand, the C.sub.s is formed over the TFT array substrate 2811. While the scan line 2801 is not selected, the TFT 2805 is turned off (high resistance state). Thus, the pixel electrode 2807 is electrically disconnected from the signal line 2803. While the scan line is selected and a voltage exceeding a lighting threshold value is applied with the electric charge to the liquid crystal layer 2815, the lighting state of the pixel is kept.
However, in the active matrix type LCD using the above-mentioned TFT, electrostatic capacitances C.sub.gs and C.sub.ds as parasitic capacitances are formed between the pixel electrode 2807 and the scan line 2801 and between the pixel electrode 2807 and the signal line 2803, respectively. With these parasitic capacitances C.sub.gs and C.sub.ds, the pixel electrode 2807 is coupled with the scan line 2801 and the signal line 2803. Thus, voltage fluctuations of the scan line 2801 and the signal line 2803 adversely affect the voltage of the pixel electrode 2807, thereby varying the voltage of noise.
In particular, when a scanning pulse goes down, a voltage fluctuation .DELTA.V.sub.p takes place and adversely affects the scan line 2801. This voltage fluctuation is referred to as a pixel voltage shift.
This voltage fluctuation .DELTA.V.sub.p is given by the following equation. EQU .DELTA.V.sub.p ={C.sub.gs /(C.sub.LC +C.sub.s +C.sub.gs +C.sub.ds)}.times..DELTA.V.sub.g
where C.sub.gs is the parasitic capacitance formed between the pixel electrode and the scan line; C.sub.LC is the capacitance of the liquid crystal layer; C.sub.s is the storage capacitance; and C.sub.ds is the parasitic capacitance formed between the pixel electrode and the signal line.
When the voltage fluctuation .DELTA.V.sub.p takes place, the voltage of the pixel electrode 2807 differs from a predetermined signal voltage applied to the signal line 2803. Thus, a signal voltage cannot be correctly applied. According to a related art reference, to solve this problem, the voltage of the opposite electrode is shifted for the voltage fluctuation .DELTA.V.sub.p so as to compensate the voltage fluctuation .DELTA.V.sub.p.
However, the capacitance C.sub.LC is not constant, but varies depending on the voltage applied to the liquid crystal and the orientation of liquid crystal molecules. In addition, due to a restriction in production, the fluctuations of the capacitances C.sub.gs, C.sub.s, and C.sub.LC in the display cannot be kept constant. Thus, on the same display, the voltage fluctuation .DELTA.V.sub.p is not constant, but varies position by position. Therefore, the voltage fluctuation .DELTA.V.sub.p cannot be satisfactorily compensated with an adjustment of the voltage of the opposite electrode disposed on opposite substrate 2813. Thus, on the display, a flickering and/or an image sticking takes place.
On the other hand, the voltage of the signal line 2803 does not accord with a picture signal voltage, but varies time by time. Thus, the voltage fluctuation of the pixel electrode 2807 affected by the signal line 2803 more frequently and variously takes place than the voltage fluctuation by the scan line 2801. As an example, under frame inversion drive, a voltage fluctuation takes place at every frame. Next, this voltage fluctuation will be described.
The polarity of the voltages of all the signal lines 2803 are inverted at every frame. Thus, when the polarity is changed, the voltages of the signal lines 2803 most largely fluctuate. The voltage fluctuation .DELTA.V.sub.ps of the pixel electrode 2807 at this point can be given by the following equation. EQU .DELTA.V.sub.ps =(C.sub.ds1 .times..DELTA.V.sub.sig1 +C.sub.ds2 .times..DELTA.V.sub.sig2)/(C.sub.LC +C.sub.s +C.sub.gs +C.sub.ds1 +C.sub.ds2)
where .DELTA.V.sub.sig1 and .DELTA.V.sub.sig2 are the voltage fluctuations of the left-side and right-side signal lines 2803 which form parasitic capacitances along with the pixel electrode 2807, respectively; and C.sub.ds1 and C.sub.ds2 are the parasitic capacitances thereof.
Whenever the polarity of the voltage of signal lines is inverted (in other words, a pixel sequence is charged at the lowest line of the display), this voltage fluctuation .DELTA.V.sub.ps takes place. Thus, a time after a signal voltage is applied until the .DELTA.V.sub.ps takes place varies vertically position by position. Thus, the brightness of the display varies position by position. This fluctuation which is referred to as the unevenness of luminance of display is observed.
When the capacitances C.sub.ds1 and C.sub.ds2 become large, the voltage fluctuation of the signal line 2803 causes the voltage of the pixel electrode 2807 to fluctuate and thereby a crosstalk takes place.
These parasitic capacitances of the TFT array substrate 2811 are formed in the following positions. The capacitance C.sub.gs is formed at overlapped portions between the channel portion of the TFT 2805 and the scan line 2801 and between the gate electrode and the pixel electrode 2807 (source electrode). On the other hand, the parasitic capacitances C.sub.ds1 and C.sub.ds2 are formed at positions where the pixel electrode 2807 and the signal line 2803 are closely disposed.
As described above, when small size and high resolution of the LCDs are accomplished and the size of one pixel is decreased, the distance between each adjacent electrode should be shortened so as to improve the open aperture ratio of the pixel and the luminance. However, when the distance between each adjacent electrode is short, the parasitic capacitances C.sub.gs, C.sub.ds1, and C.sub.ds2 disproportionally increase. Thus, the unevenness of luminance and crosstalk frequently take place, thereby degrading the picture display quality.
In addition, to prevent the contrast of the pixel from degrading due to penetration of rays of light to the opening between the scan line 2801 and the signal line 2803 and between the scan line 2801 and the pixel electrode 2807 and to prevent the TFT 2805 from malfunctioning due to an leakage current caused by rays of light entered thereto, a light shielding film referred to as a black matrix or a black mask is conventionally used. Normally, the black matrix is disposed on the opposite substrate side. When the TFT array substrate 2811 and the opposite substrate 2813 are oppositely disposed, the opening portion of the black matrix is opposed to the opening portion of pixel electrode.
However, when the size of each pixel is further decreased due to small size and high resolution of the LCD, it is necessary to form a pixel electrode and a black matrix in a finer pattern size and with a higher accuracy so as to improve the open aperture ratio of the pixel and the brightness thereof. In addition, the opposite substrate 2813 and the TFT array substrate 2811 should be more finely aligned. Thus, the production of the LCD becomes more difficult.
When the size of each pixel is decreased, the pattern accuracy and the alignment tolerance of the pixel electrode and the black matrix become strict and severer. Thus, their production becomes harder and harder.
In addition, in the overlap of the storage capacitor electrode 2809 and the pixel electrode 2807, a shortcircuit and a current leak sometimes take place. Thus, display defects such as point defects occasionally occur. Due to these display defects, the yield of the production of the conventional active matrix type LCDs was low. In particular, the storage capacitor electrode 2809 was devised so as to keep a good picture display for a predetermined long time. However, as described above, since display defects such as point defects took place, the conventional LCDs had a practical problem.